With the continuous development in IC (integrated circuit) manufacturing technology, the feature size of a MOSFET (metal-oxide-semiconductor field-effect transistor) continuously shrinks. In order to reduce parasitic capacitance on the gate electrode of a MOSFET and increase device speed, a gate stack structure that includes a high-K (high dielectric constant) gate dielectric layer and a metal gate electrode is introduced to the MOSFET. In order to prevent the metal material of the metal gate electrode from affecting the other structures of the transistor, the gate stack structure including a metal gate electrode and a high-K gate dielectric layer is generally manufactured by a gate-last process.
The gate-last process includes: providing a semiconductor substrate, on which a dummy gate structure and an etch stopping layer covering the dummy gate structure are provided; forming an interlayer dielectric layer on the surface of the etch stopping layer; performing CMP (chemical-mechanical polishing) on the interlayer dielectric layer and the etch stopping layer by using the surface of the dummy gate structure as a stopping layer; removing the dummy gate structure to form a trench; filling in the trench with metal by PVD (physical vapor deposition) or sputtering the metal from a target to the trench, to form a metal gate electrode layer; and polishing the metal gate electrode layer by CMP until the interlayer dielectric layer is exposed, thereby a metal gate is formed.
Accordingly, in the gate-last process, the manufacture of the dummy gate is crucial. However, currently, due to the limitations in physical mechanism, processing technology, manufacturing techniques, etc., the critical dimension of the dummy gate and the profile of the dummy gate cannot be accurately controlled at the 22 nm node and beyond, which degrades gate LER (Line Edge Roughness), device performance and device reliability.